By Anthony J.G. Hey
A tribute to Feynman and a brand new exploration of the bounds of pcs via a few of cutting-edge such a lot influential scientists.
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Additional info for Feynman and computation: exploring the limits of computers
SIMULATION ISSUES Perhaps the most important phase of chip design, and the most often overlooked phase, is that of simulation. Simulation can save many frustrating hours debugging a chip in your system. Doing a good job at simulation uncovers errors before they are set in silicon, and can help determine that your chip will function correctly in your system. There are two main aspects of your design for which simulation is used to determine correctness - functionality and timing. Functionality refers to how the chip functions as a whole, and how it functions in your system.
Similarly, outputs must be disabled while the chip is being scanned since dangerous combinations of outputs may be asserted that can harm your system. There are other considerations, also, such as what to do with the clock and what to do with the rest of the system while the chip is being scanned. 35 Introduction to FPGA Design Figure 35 Scan Methodology Boundary scan is somewhat easier to implement and does not add as much logic to the entire chip design. Boundary scan only scans nodes around the boundary of the chip, but not internal nodes.
Also, for simulation purposes, simulation software needs to start out from a known state before useful results can be obtained. 3 Observable Nodes As many nodes as possible in your chip design should be observable. In other words, it should be possible to determine the values of these nodes using the I/O pins of the chip. On the left side of Figure 34, an unobservable state machine is shown. On the right side, the state machine has been made observable by taking each state machine through a mux to an external pin.
Feynman and computation: exploring the limits of computers by Anthony J.G. Hey